ASIC VLSI Design Course A modern VLSI chip has grown remarkably to implement very complex designs, with today technology advent each chip holds billions of transistors, millions of logic gates deployed for computation and control, huge memory blocks, embedded functional blocks with pre-designed functions designed by third parties. How can engineer manage to handle such complex design in today's semiconductor technology? And the answer to this lies in advent of HDL's and EDA tools support, core functionality is described using HDL's and EDA tools takes an abstract description of the chip, and translates to logic gates a final design. This class focuses on various HDL's that will be taught during this course, along with design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus is on the key representations that make it possible to synthesize, and to verify, these designs, as they move from logic to layout. is theFront end RTL Design Course that imparts knowledge in ASIC design flows from basic architecture and trains the engineers extensively on the VLSI design methodologies, RTL coding and Digital Synthesis process. Full front end design flow is taught along with digital logic fundamentals.
1. Introducton to VLSI Design
2. Advanced Digital Design Concepts
3. CMOS Logic fundamentals
4. RTL Design with Verilog HDL's
5. ASIC Design Systhesis Concepts
6. ASIC Design Stratagies
7. Static Timing Analysis
8. Low power design implementation
9. Design and power Constraints
10. Perl/Shell Scripting
11. EDA tools usage
12. Live Projects
Programming experience (C/C++) and understanding of basic digital design, Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Exposure to basic VLSI at an undergraduate level is recomended.
The course is designed to be self-contained. However, we will offer pointers to original source material, i.e., papers in conferences and journals. Text book materials, that covers logic and layout, as well as representation, optimization, synthesis and verification. So, we will work to be as complete as possible in the lectures.
The class will consist of class room lecture, duration of each class is 1 hr weekly 6hrs of class room teaching. Assignment, Labs and project work will be worked in seperate classes, lab access is unlimited.
To explore Digital logic design fundamentals and demonstrate RTL coding using Verilog/VHDL. To explain chip design with CMOS fundamentals, covers various design techniques to meet area, power and timing requirements.