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VLSI Training

 

Overview

ASIC VLSI Design Course A modern VLSI chip has grown remarkably to implement very complex designs, with today technology advent each chip holds billions of transistors, millions of logic gates deployed for computation and control, huge memory blocks, embedded functional blocks with pre-designed functions designed by third parties. How can engineer manage to handle such complex design in today's semiconductor technology? And the answer to this lies in advent of HDL's and EDA tools support, core functionality is described using HDL's and EDA tools takes an abstract description of the chip, and translates to logic gates a final design. This class focuses on various HDL's that will be taught during this course, along with design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus is on the key representations that make it possible to synthesize, and to verify, these designs, as they move from logic to layout. is theFront end RTL Design Course that imparts knowledge in ASIC design flows from basic architecture and trains the engineers extensively on the VLSI design methodologies, RTL coding and Digital Synthesis process. Full front end design flow is taught along with digital logic fundamentals.

Course Syllabus

1. Introducton to VLSI Design
2. Advanced Digital Design Concepts
3. CMOS Logic fundamentals
4. RTL Design with Verilog HDL's
5. ASIC Design Systhesis Concepts
6. ASIC Design Stratagies
7. Static Timing Analysis
8. Low power design implementation
9. Design and power Constraints
10. Perl/Shell Scripting
11. EDA tools usage
12. Live Projects

Recommended Background

Programming experience (C/C++) and understanding of basic digital design, Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Exposure to basic VLSI at an undergraduate level is recomended.

Suggested Readings

The course is designed to be self-contained. However, we will offer pointers to original source material, i.e., papers in conferences and journals. Text book materials, that covers logic and layout, as well as representation, optimization, synthesis and verification. So, we will work to be as complete as possible in the lectures.

Course Format

The class will consist of class room lecture, duration of each class is 1 hr weekly 6hrs of class room teaching. Assignment, Labs and project work will be worked in seperate classes, lab access is unlimited.

Objectives

To explore Digital logic design fundamentals and demonstrate RTL coding using Verilog/VHDL. To explain chip design with CMOS fundamentals, covers various design techniques to meet area, power and timing requirements.

Overview

This intensive, practical course is intended for fresh graduates and experienced Engineers interested in the latest design verification enhancements to SystemVerilog, course designed for Verification/RTL Design Engineers, course modules are designed by IISc/IIT Alumnis with decades of industry expertise. The course is designed as per current industry requirements and will be taught by Senior Engineer with 10+ years of Design Verification Experience.
Importances is given to while teaching on best-practice usage of SystemVerilog features like Object Oriented programming, Constrained Randomization and Functional Coverage. completely covering the verification concepts and methodology thoroughly with good emphasis on testplan creation and development with hands-on labs, while latest EDA tools in labs.

Course Syllabus

1. Introduction to Verification Languages
2. Verification Tools
3. Verification Process in ASIC Flow
4. Timing Verification Process.
5. Test-Bench Automation
6. Introduction to SystemVerilog
7. Random vs. directed testing
8. Functional coverage
9. Object Oriented programming
10. DPI Concepts
11. EDA tools usage
12. Live Projects

Recommended Background

Programming experience (C/C++) and understanding of basic digital design, Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Attendees must be familiar with Verilog and ideally, but not essentially, Verilog2001. No prior knowledge of SystemVerilog is required. Exposure to basic VLSI at an undergraduate level is recomended.

Suggested Readings

The course is designed to be self-contained. However, we will offer pointers to original source material, i.e., papers in conferences and journals. Text book materials, that covers verification concepts and systemverilog language. So, we will work to be as complete as possible in the lectures.

Course Format

The class will consist of class room lecture, duration of each class is 1 hr weekly 6hrs of class room teaching. Assignment, Labs and project work will be worked in seperate classes, lab access is unlimited.

Objectives

To explore the new features of SystemVerilog for verification and demonstrate the improvements in verification environment efficiency from their use.
To explain key features for verification, such as classes, OOP, randomization, and functional coverage and illustrate how to exploit these features for more efficient verification and testbench development

Overview

This intensive, practical course is intended for fresh graduates and experienced Engineers interested in the latest design verification enhancements to SystemVerilog, this course covers UVM methodology which is advanced verification concept. This course designed for Verification/RTL Design Engineers, course modules are designed by IISc/IIT Alumnis with decades of industry expertise. The course is designed as per current industry requirements and will be taught by Senior Engineer with 10+ years of Design Verification Experience.
Importances is given to while teaching on best-practice usage of SystemVerilog and UVM features like Object Oriented programming, Constrained Randomization, Functional Coverage and verification methodologies. completely covering the verification concepts and methodology thoroughly with good emphasis on testplan creation and development with hands-on labs, while latest EDA tools in labs.

Course Syllabus

1. Introduction to Verification Languages
2. Verification Tools
3. Verification Process in ASIC Flow
4. Timing Verification Process.
5. Test-Bench Automation
6. Introduction to SystemVerilog
7. Random vs. directed testing
8. Functional coverage
9. Object Oriented programming
10. DPI Concepts
11. UVM Based verification
12. TLM Basics
13. UVM Environment
14. EDA tools usage
15. Industry standard live Projects

Recommended Background

Programming experience (C/C++) and understanding of basic digital design, Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Attendees must be familiar with Verilog and ideally, but not essentially, Verilog2001. No prior knowledge of SystemVerilog is required. Exposure to basic VLSI at an undergraduate level is recomended.

Suggested Readings

The course is designed to be self-contained. However, we will offer pointers to original source material, i.e., papers in conferences and journals. Text book materials, that covers verification concepts and systemverilog language. So, we will work to be as complete as possible in the lectures.

Course Format

The class will consist of class room lecture, duration of each class is 1 hr weekly 6hrs of class room teaching. Assignment, Labs and project work will be worked in seperate classes, lab access is unlimited.

Objectives

To explore the new features of SystemVerilog and UVM based verification and demonstrate the improvements in verification environment efficiency from their use.
To explain key features for verification methodologies, using some of the key features such as classes, OOP, randomization, and functional coverage and illustrate how to exploit these features for more efficient verification and testbench development

Overview

Neoschip Semiconductors is one of the best institutes in India with an object to provide industry leading training program in “VLSI Physical Design” for Ultra low power nano scale designs, course structure is designed and targeted to use latest industry and standard EDA tools. In industry there is gap between individuals and trained professionals, with this course it will help to fill the gap of trained manpower in the semiconductor industry which is budding stage in India.
Neoschip Semiconductors is managed by professionals from IISc/IIT's Alumni's with over 15+ years of rich VLSI design experience, our course curriculum is designed in keeping view on students ability in understanding the advanced concepts in very simpler way and to impart strong fundamentals in chip designing.
All the lectures will be delivered by experts in physical design, trainers having rich experience with ample importance is given to cover the fundamentals concepts, chip design methodology thoroughly with good emphasis on hands-on training, there are seperate classes to cover theory and lab session. More than 60% of the course training imparted while doing labs, that way aspiring engineers can get more practical knowledge.
Our institute transforms fresh engineers into full ASIC Physical Design Engineer, while meeting industry requirements, Hands-on practice of concepts learned on progressively complex designs strengthens the skills and the course finishes with a mini-project.

Course Syllabus

1. Introduction to VLSI Digital Design
2. Semiconductor technologies and CMOS fundamentals
3. ASIC design flow and design planning
4. ASIC design standard cell libraries and flow setup
5. Review synthesis principles and synthesis of design modules
6. Pre-Layout design partitioning and planning
7. Design floor planning and power planning
8. Design Placement
9. Clock tree synthesis and timing analysis
10. Routing
11. Detailed timing analysis and optimizations, parasitic extraction
12. Post route design checks and signoff
13. Shell/Perl Scripting
14. EDA tools usage
15. Industry standard live Projects

Recommended Background

All fresh and experienced professionals having 65% or above with good academics and with major subject as electronics

Suggested Readings

The course is designed to be self-contained. However, we will offer pointers to original source material, i.e., papers in conferences and journals. Text book materials, that covers cmos fundamentals anddigital logic implementation. So, we will work to be as complete as possible in the lectures.

Course Format

The class will consist of class room lecture, duration of each class is 1 hr weekly 6hrs of class room teaching. Assignment, Labs and project work will be worked in seperate classes, lab access is unlimited.

Objectives

Getting hands on experience in complete chip design flow from RTL netlist to GDSII, reviewing design methodologies to meet performance goals at various stages in ASIC Design Layout. Its 60% labwork with 4 to 5 projects to work.

Overview

Covers fundamental concepts in Digital Designs,CMOS basics, ASIC layout fundamentals, semiconductor process technologies, combinational logic, sequential logic, Asyncronous CDC techniques, power aware design techniques, timing analysis, RTL to gateslogic synthesis fundamentals, ASIC floor planning, place & route, clock tree synthesis, signal integrity, IR-drop analysis, Static Timing Analysis, low power design techniques and so on..

Objectives

Getting hands on experience in complete chip design flow from RTL netlist to GDSII, reviewing design methodologies to meet performance goals at various stages in ASIC Design Layout. Its 60% labwork with 4 to 5 projects to work.

Overview

Covers fundamental concepts in Digital Designs,CMOS basics, ASIC layout fundamentals, semiconductor process technologies, combinational logic, sequential logic, Asyncronous CDC techniques, power aware design techniques, timing analysis, RTL to gateslogic synthesis fundamentals, ASIC floor planning, place & route, clock tree synthesis, signal integrity, IR-drop analysis, Static Timing Analysis, low power design techniques and so on..

Objectives

Getting hands on experience in complete chip design flow from RTL netlist to GDSII, reviewing design methodologies to meet performance goals at various stages in ASIC Design Layout. Its 60% labwork with 4 to 5 projects to work.

Overview

Covers fundamental concepts in Digital Designs,CMOS basics, ASIC layout fundamentals, semiconductor process technologies, combinational logic, sequential logic, Asyncronous CDC techniques, power aware design techniques, timing analysis, RTL to gateslogic synthesis fundamentals, ASIC floor planning, place & route, clock tree synthesis, signal integrity, IR-drop analysis, Static Timing Analysis, low power design techniques and so on..

Objectives

Getting hands on experience in complete chip design flow from RTL netlist to GDSII, reviewing design methodologies to meet performance goals at various stages in ASIC Design Layout. Its 60% labwork with 4 to 5 projects to work.

Overview

Covers fundamental concepts in Digital Designs,CMOS basics, ASIC layout fundamentals, semiconductor process technologies, combinational logic, sequential logic, Asyncronous CDC techniques, power aware design techniques, timing analysis, RTL to gateslogic synthesis fundamentals, ASIC floor planning, place & route, clock tree synthesis, signal integrity, IR-drop analysis, Static Timing Analysis, low power design techniques and so on..

Objectives

Getting hands on experience in complete chip design flow from RTL netlist to GDSII, reviewing design methodologies to meet performance goals at various stages in ASIC Design Layout. Its 60% labwork with 4 to 5 projects to work.

Overview

Covers fundamental concepts in Digital Designs,CMOS basics, ASIC layout fundamentals, semiconductor process technologies, combinational logic, sequential logic, Asyncronous CDC techniques, power aware design techniques, timing analysis, RTL to gateslogic synthesis fundamentals, ASIC floor planning, place & route, clock tree synthesis, signal integrity, IR-drop analysis, Static Timing Analysis, low power design techniques and so on..

Objectives

Getting hands on experience in complete chip design flow from RTL netlist to GDSII, reviewing design methodologies to meet performance goals at various stages in ASIC Design Layout. Its 60% labwork with 4 to 5 projects to work.

Overview

Covers FPGA design fundamentals, RTL design methodologies, Digital logic fundamentals amd FPGA requirements, FPGA vendors, FPGA tools, PNR, performance analysis tool flow. Mapping techniques for soft and hard IP's in FPGA. Synthesis, implementation and bitstream generation.

Objectives

By end of this course, students will be in position to design RTL for FPGA's and can succefully generate FPGA implemented designs.

Advanced PCB Schematic and Layout design course

For any electronics product, printed circuit board (PCB) forms the basic foundation for interconnecting and packaging. PCBs are used to mechanically support and electrically connect electronic components using conductive pathways, tracks or signal traces etched from copper sheets laminated on a non-conductive substrate (source: Wikipedia). PCBs are also referred to as printed wiring boards (PWBs), or etched wiring boards, which have evolved over the years from uncomplicated single- and double-sided plated-through-hole (PTH) to become multi-layered PCBs. Click here to know more details

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Training Requirement

Teaching Faculty

All of our teaching faculty holds a Master Degree from IIT with specialization in VLSI and Embedded systems with relevant industrial experience from 4 to 10 years.All are exposed to industry requirement as all are from the industry (Senior Consultant Level). They also have good project execution exposure and hands on experience on various tools use in the training programs. The whole team is well motivated to imaprt quality training to build knowledge levels of students.

 

Contact Details

NeoChip Semiconductors

3rd Floor, Sai Durga Enclave, 1099/833-1,
Marathahalli-Sarjapur Outer Ring Rd,
Bellandur, Bengaluru, Karnataka 560103

Phone :
Mobile : +91 7095224400
Email : info@neoschip.com

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