This course is designed to help VLSI career aspirants in the field of VLSI Analog Layout Design. It covers complete details from VLSI CMOS concepts, Mos transistor basics, fabrication technologies, complete details on analog custom layout design flows, this course helps to acquire suffiecient skills as needed by Industry. Course modules are designed as per Industry needs and provides complete indepth knowledge to handle challenges in VLSI Analog layout Flow. Aspiring candidates will learn complete knowledge from circuit netlist to Analog layout till GDS2 generation, all lab sessions enables students to work on advanced lower nanometer technology nodes. The course will benefit VLSI Engineers seeking to enter into VLSI Analog layout engineer job. In this role engineers will be working for Block & full chip level Analog layout Design Implementation.
The main focus of the course is to make each engineer understand physical design of IC from netlist through GDSII, creating physical layout representation for each analog functions with in blocks to enable IC fabrication process.
While in course work, for every candidate more emphasis is given on learning through practicals backed by theoritical concepts taught during classes & in the lab sessions.
Eligibility
With Electronics as major subject in B.E/B.Tech/M.E/M.Tech, atleast 60% throughout academic
career. Basic knowledge in Verilog/VHDL, Good knowledge on Digital design, Good knowledge
on any Microcontroller/Processor architectures, and Good logical & analytical ability
Selection based on written test and personal Interviews for eligible interested Candidates.
Syllabus for written test covers Electronic Devices & circuits, and Analytical and
Logical questions. Please walkin/mail/call us to schedule for written test & personal interview.
Working VLSI/Software
professionals will get direct admissions.
Course Outline
• Basics of analog circuit design concepts
• Analog circuit design challenges and implementation strategies
• Introduction to Analog layout concepts
• Layout design rules and process
• Introduction to fabrication techniques
• Ionization and wafer technology
• CMOS/BJT/MOSFET/FINFET IC fabrication steps
• Fabrication techniques for Deep submicron technology
• Understanding various mask layers
• Layout requirements for each layers
• Layout floor planning
• BUMP/PAD/ESD/PIN planning
• Creating libraries, adding and managing layout cell views
• Creating config views for DRC/LVS checks
• Layout editor tool commands and shortcuts
• Commands for creating netlist from schematics and exporting to layout view
• Layout spice simulation commands
• Layout of basic CMOS gates, INV, AND, NAND, OR, NOR
• Complex cell layout design
• Orientations
• Multifingers/common Centriod/Quads
• Distance/Gaps between layout layers
• Overlaying and Adjacent layers
• Same Area/Perimeter ratios
• soft edge shapes
• DRC/ERC/LVS soft checks
• Electro migration checks and Removal techniques
• IR Drop analysis
• Antenna affect checks and Removal techniques
• SI checks like crosstalk and EMI issues
• ESD checks and ESD cell designs
• Dish effects checks and removal
• Well proximity checks
• Analog Amaplifiers, comparators, filters circuits
• Opamp sense amplifier designs
• Differential Opamp Designs
• Bandgap layout Designs
• BUMP/ESD/Gaurd ring designs
• Tap Cell Designs
• SRAM cell design
• Rows and Columns Decoders
• Sense Amplifier design
• Write/read control logic
• Power supply design
• Dual port RAM cell designs
• PLL, LDO, ADC layouts. In 65nm, 32nm, 14nm
• Assignments given for Lab practice
Viswanath Reddy
Very well designed course curriculam, teaching faculty well experienced in Analog Layout designs.